Patterns in an integrated circuit are designed according to requirements of circuit performance, layout and routing. The output of layout and routing is a set of target polygons that are input to photomask design. The goal of photomask design is to minimize the difference between the pattern that will be rendered on the wafer, and the target pattern, for a sufficiently large process window. Process window refers to a region in the exposure dose-defocus plane on which one or more critical dimension of a pattern is printed within an acceptable tolerance. Photomask design is an optimization process. Resolution enhancement techniques (RET) and optical proximity corrections (OPC) are techniques that are used to optimize the photomask for a given target pattern.
An important consideration in chip design is that not every pattern can be rendered by lithography. It is entirely possible to specify a target pattern that is not printable, or printable with an unacceptably narrow process window, using a specific lithography process.
Layout and routing is constrained by a set of geometric design rules. For example, design rules may include minimum line width, minimum space width, disallowed combinations of line and space widths. Conformance of a target pattern to design rules is performed by a design rule check (DRC) software, which is based on geometry operations. A set of design rules is specific to a certain combination of wavelength, numerical aperture of the lithography projector, illumination condition, and photoresist. Design rules are selected to ensure that if a pattern conforms to the design rules, the pattern will be printable with a sufficient process window.
However, design-rule checking of the prior art has deficiencies and limitations, including the following: (1) there is no guarantee that a finite set of geometric rules can predict printability of countless two-dimensional patterns; (2) if design rules ensure printability, they may be overly conservative and may lead to increased chip size; (3) designers may choose to violate design rules to achieve a higher density of devices, for example in an SRAM design.
If design rules are bypassed or design rules unwittingly allow a pattern that is not printable, RET and OPC can be thrown into an endless loop. If an RET/OPC approach fails to achieve a desired target pattern and process window, the natural reaction of the RET/OPC engineer is to change the parameters of optimization, or to consider different RET schemes. This process can waste precious design time because prior art RET/OPC cannot definitively state that a certain target is unprintable irrespective of photomask technology at a given wavelength and numerical aperture (NA).
The prior art includes determination of printability after applying optical proximity corrections to the photomask layout (see: Choi et al., Proceedings of SPIE, Vol. 5377, p. 713-720, SPIE Bellingham, Wash., 2004).
It is among the objects of the present invention to provide a technique for determining when the result of optical proximity corrections will fail to meet the design requirements, without having to perform the optical proximity corrections. It is also among the objects of the present invention to improve on existing techniques for checking the printability of a lithography target layout. [As used herein, “printability” of a target layout means that when the layout is employed in projecting an image on the wafer, the pattern that is printed (for example, on a photoresist film coating of a wafer) by exposure with optical radiation, has acceptable tolerances.]